The present invention relates to a semiconductor device and more particularly an integrated semiconductor device with resistor elements formed by a gate array system.
Nowadays, the semiconductor integrated circuit has been well developed and various kinds of semiconductor devices having very complicated function are manufactured economically in a mass production scale by using finely formed mask patterns. Contrary to this, when semiconductor devices for special use are manufactured in a small scale, use is generally made of a manufacturing technique such as a master slice approach and a gate array system, because mask patterns cannot be formed economically.
In the gate array system, at first basic integrated circuits are formed. The basic integrated circuit includes number of function cells including active elements such as bipolar transistors and MOS transistors and wiring cells called a cross-under, the active cells and wiring cells being arranged regularly. Then these active cells and wiring cells are selectively connected by a wiring process to form a desired logic circuit. In this manner, a given semiconductor device is obtained.
FIG. 1 is a schematic view showing an example of an arrangement of active cells and wiring cells of such a semiconductor device formed by the gate array system. The device comprises active cell regions 1a to 1d each including bipolar transistors and MOS transistors and wiring cell regions 2a to 2d. The active cell regions are connected by means of the wiring cell regions. As illustrated in FIG. 1, the active cell regions 1a to 1d and wiring cell regions 2a to 2d are arranged alternately in a regular manner.
FIG. 2 is a plan view showing part of the active cell regions and wiring cell regions in an enlarged scale. In the active cell region 1a there are formed active cells 11 to 14 and in the active cell region 1c there are formed active cells 15 to 18. In FIG. 2, the active cells 11, 12 15 and 16 are P channel MOS transistors and active cells 13, 14, 17 and 18 and N channel MOS transistors. Each active cell is composed of a series circuit of two MOS transistors. The active cells may be constructed in different ways. For instance, each cell may be formed by one or more than two transistors or may be composed of one or more bipolar transistors.
In the wiring cell region 2a there are formed a plurality of wiring cells 21 to 26 arranged in parallel with each other. Each of the wiring cells 21 to 26 has a strip-shaped P type impurity diffusion layer called a cross-under serving as a conductor connecting active cells to each other. Surfaces of the active cell regions 1a to 1d and wiring cell regions 2a to 2d are covered with an insulating layer 30 consisting of SiO.sub.2. In the SiO.sub.2 layer 30, openings are formed at positions corresponding to given electrode portions of the active cells and wiring cells by means of a known photo-etching process. Then, aluminum electrode contacts 31 to 34 are formed via the openings, on the electrode portions.
Then aluminum conductors 41 to 44 are deposited on the insulating layer 30, while portions of the conductors are selectively connected to the electrode contacts to form a required logic circuit.
As can be read from FIG. 2, the wiring cells of the gate array system have a function to avoid possible short circuits of the deposited conductors on the insulating layer 30 and to make simple the wiring operation. For instance, when the electrode contacts 31 and 33 are connected by means of the conductor 41 and the electrode contacts 32 and 34 are connected by the conductor 42, it is possible to couple the electrode contact 33 of the active cell 11 and the electrode 34 of the active cell 17 with each other by means of the wiring cell 22 in the wiring cell region 2a without being short-circuited with the wiring conductors 43 and 44 on the insulating layer 30. In this manner, in the gate array system, the wiring cells are exclusively used as the connecting wires for connecting the active cells. However, in practice all the wiring cells are not used for the connection and the wiring cells 21, 23 and 24 are not used in the finally obtained semiconductor integrated circuit.
In the known semiconductor device of the gate array system, when it is required to include resistance elements such as potentiometers, necessary resistors are connected externally, because in the basic semiconductor device there is not formed any resistance elements. Therefore, the manufacturing steps are increased and thus, the reliability of the device becomes low and the size of the device becomes large.